Latest Intel processor could steal the ISSCC show

SAN FRANCISCO — Intel Corp. will come to the International Solid-State Circuits Conference this week with tips for reining in runaway power as chip integration rises, following up on the call to arms it sounded at last year's ISSCC. Intel technology executives last week briefed analysts on techniques applied in the McKinley processor architecture as well as on such speculative technologies as body biasing and a new nonvolatile memory that could displace flash in cell phones and other space-constrained portables.

"Once a geek, always a geek," Pat Gelsinger, Intel's chief technology officer, joked as he described the topics Intel would broach at the conference. Gelsinger's keynote address last year had warned that Moore's Law would not only advance silicon integration but also bring on exponential increases in power consumption. In addition to biasing techniques that achieve faster clocks and higher yields with lower voltage levels, Intel's technologists previewed a processor that would integrate 291 million transistors.

That device, code-named McKinley, has been sampling since last February and is slated to enter production around midyear, said Intel fellow John Crawford, director of the McKinley architecture project. Intel and co-developer Hewlett-Packard Co. will jointly present six papers at ISSCC, most of them revolving around McKinley's cache and circuit designs. The 3-Mbit Level 3 cache, for example, achieves 85 percent efficiency (compared with 70 percent for traditional cache designs) while consuming 20 percent less silicon area.

The 64-Gbits/second L2 cache bandwidth is up to 4x greater than that of proprietary RISC processors. The L1 cache — the one closest to the core — has a one-cycle latency that provides a 15 to 25 percent performance increase over typical, two- to three-cycle-latency designs. Elimination of load delay penalties simplifies compiler scheduling, Crawford said.

McKinley provides a 1.5x to 2x performance increase over the 64-bit Itanium architecture, Crawford said. Not all the boosts are due to the on-chip L3 cache: The bus width on McKinley (128 bits) is double that of other Itanium family members, and its transfer rate has been increased from 266 MHz to 400 MHz. Additional execution units more than compensate for a somewhat shorter instruction pipeline.

There is also better support for branch instructions and for concurrent load and store operations. Finally, the central core of McKinley will run at 1 GHz, an advance on the 800-MHz core of Itanium.

Separately, Intel's work on body bias techniques — performed in conjunction with the Massachusetts Institute of Technology — may have a profound effect on semiconductor manufacture.

Manufacturers have long known that the n- or p-well tub in which a CMOS transistor sits can form a diode (a conductive path) to the bottom of the chip. Ordinarily, that body diode forms a blocking function, but researchers have observed interesting effects when the diode is tweaked or biased with small amounts of current.

As explained by Justin Rattner, Intel Fellow and director of Microprocessor Research at Intel Labs, body bias techniques can raise the performance of the surface transistor while letting it operate at low voltage levels. As will be reported at ISSCC this week, Intel discovered that a 450-millivolt forward bias on a 1-GHz device could reduce power consumption by as much as 23 percent. The 1-GHz test chip operated well at 1.1 V, Rattner said.

The same device, operated without bias, required 1.25 V to get it to clock at 1 GHz.

Most dramatic were the effects of biasing on manufacturing yields. Presumably, dead transistors would spring to life with a little body bias. Thus, wafer yields approached 100 percent with certain performance targets.

In products, body bias could be adaptive and self-adjusting, Rattner said. While extra circuitry would be required to apply the bias, he estimated that it would take up no more than an extra 1 or 2 percent of the die area.

Intel used a 5-GHz, 32-bit integer math core to have what Rattner called a "processor-level look" at the bias technology. But it may be years (with the advent of 90- or 60-nm technology) before full-blown processors would run at that speed.

Equally as speculative is a nonvolatile memory being studied as a replacement for flash. The ovonics unified memory uses a polycrystalline chalcogenide layer to retain impressions (or bits) burned in by a resistive heater element, said Stefan Lai, vice president and co-director of Intel's California Technology and Manufacturing group. The chalcogenic layer combines germanium, antimony and tellurium, allowing memory impressions can be rewritten several thousand times.

Intel had reported on these experiments at IEDM in December. The current ISSCC presentation reports on attempts to build a 4-Mbit memory device with the new memory technology. Intel is pleased with the density and foresees compatibility with 0.13-micron manufacturing processes, Lai said.

The drawback for now is current consumption, which exceeds 1 milliamp per cell on 0.18-micron geometries.